SPI1 flash suspend control register
| SPI_MEM_FLASH_PER | program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. |
| SPI_MEM_FLASH_PES | program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. |
| SPI_MEM_FLASH_PER_WAIT_EN | 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent. |
| SPI_MEM_FLASH_PES_WAIT_EN | 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent. |
| SPI_MEM_PES_PER_EN | Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done. |
| SPI_MEM_FLASH_PES_EN | Set this bit to enable Auto-suspending function. |
| SPI_MEM_PESR_END_MSK | The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0]. |
| SPI_FMEM_RD_SUS_2B | 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit |
| SPI_MEM_PER_END_EN | 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0. |
| SPI_MEM_PES_END_EN | 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0. |
| SPI_MEM_SUS_TIMEOUT_CNT | When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass. |